With the rapid advancement in memory technology, computer systems must be developed for current technologies and they must also continue to support previous technologies. For desktop and other computer systems, memory technology has advanced from DRAMs (Dynamic Random Access Memories) to SDRAMs (Synchronous DRAMs). With DRAM technology, many actuating signals for example, are generated only after earlier timing signals have been provided when the actuating signals are derived from the earlier timing signals. Accordingly, timing was not a critical consideration for most applications. However, with synchronous systems, and particularly with SDRAMs, signal propagation is accomplished in strict accordance with clock signals and all timing and actuation signals must be completed at a particular predetermined time relative to a main clock signal. Thus, with the faster synchronous systems, timing becomes extremely critical.
With reference to memory systems, it is noted that the desktop computer industry has standardized on DIMM (Dual In-line Memory Modules) devices as the basic memory component. In particular, the popular DIMM for many computer systems is the 168 pin DIMM. For DRAM DIMMS, the DIMM has pin connections or pads to receive first and second WE (Write Enable) signals from a memory controller. Most memory system implement a set or plurality of DIMMs juxtaposed on a memory card. Typically, the WE line from a memory controller on the memory card is run along a common line from the memory controller to each of the first WE pads of the DIMM set, and then continues in a common line to be connected to each of the second WE pads on the same set of DIMMs. Since the first and second WE pads are typically some distance from each other, even though this method of series connections has not been a problem for DRAM DIMMs, it has resulted in many unnecessarily long transmission lines in many computer systems. Such long transmission lines do, however, present timing problems when it is desired to upgrade such memory systems to SDRAMs. The timing requirements for SDRAMs are much tighter than they are for DRAM technology since every operation must occur synchronously with the clock signal for the memory slot.
Thus, there is a need for an improved method and implementing system for accommodating signal timing requirements for both DRAM technology as well as for the relatively faster SDRAM technology.